1. Field of the Invention
The present invention provides a process for the simultaneous production of bipolar transistors and complementary MOS transistors on a common substrate utilizing known technology for the production of n- and p-doped zones, double-polysilicon-gate technology, and the production of npn-bipolar-transistors positioned in n-doped zones.
2. Description of the Prior Art
The present invention relates in particular to a process wherein the n-zones in which the bipolar transistors are positioned form the collector of the transistor and cover buried n.sup.+ -doped zones which are connected in the bipolar transistor zone by deep extending collector terminals.
A process of this type for 1 micron well CMOS bipolar technology for highly integrated circuits is disclosed, for example, in an article by Miyamoto et al in the IEDM 1983, Technical Digest, pages 63 to 66. A buried collector connected by a deep collector contact is used to reduce the collector resistance.
A 2 micron CMOS bipolar technology is also disclosed in an article by Alvarez et al in the IEDM 1984 Technical Digest on pages 761 to 764.
The production of a bipolar transistor which has a buried collector and self-aligned base-emitter zones, the emitter and base zones being formed by diffusion out of doped polysilicon structures, is disclosed in an article by Murrmann entitled "Modern Bipolar Technology for High Performance ICs" in the Siemens Research and Development Reports, Vol. 5 (1976), No. 6, pages 353 to 359 and in an article by Wieder entitled "Self-Aligned Bipolar Technology--New Chances for Very-High Speed Digital Integrated Circuits" in Siemens Researach and Development Reports, Vol. 13 (1984), pages 246 to 252. Transistors of this type are used in LSI circuits for high switching speeds.